1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that has a defective block.
2. Description of the Related Art
NAND-type flash memories and AND-type flash memories are allowed to have an initial defect block including defective bits, being different from NOR-type flash memories. In order to notify users of addresses of initial defective blocks, the manufactures write data “00h” in the entirety of a predetermined area of each initial defective block. This predetermined area in any non-defective block has the entirety thereof in an erased state, and has “FFh” stored therein. Users read data from the predetermined area, and check whether the retrieved data are all “FFh”. If any one piece of the data read from the predetermined area is not “FFh”, then, the block is ascertained as a defective block.
Blocks ascertained as being defective are controlled in a list format by a control-end device such as a memory controller, a CPU, or the like by using a list that indicates defective blocks. In detail, a check is made in an apparatus using a flash memory as to whether all the bytes are “FFh” by reading data from all the predetermined areas of all the blocks. When a defective block is detected, data of a defective block address is stored in the flash memory itself or another memory device by using a predetermined table format or the like. When the flash memory itself is used during normal operations, the address information indicative of defective blocks is referred to, and control is attended to so as not to access the defective blocks.
In the configuration in which defective blocks are controlled as described above, data that are in existence at the time of shipping out from factories will be lost once the memory is used. When there is a need to use a memory in a system after having used the memory in another system, there is no way of knowing the positions of defective blocks by inspecting the data of the memory.
In NAND-type flash memories and AND-type flash memories, there is a possibility of a new defect developing after shipping out from factories. If an ECC error is detected when reading data from a block that is supposed to be non-defective, this block is registered as a subsequently acquired defect block, and no access thereto will be made thereafter. In this manner, there are initial defective blocks and subsequently acquired defective blocks, and different detection processes need to be carried out for the respective types of blocks. This makes the control of defective blocks prohibitively complicated.
Accordingly, there is a need for a semiconductor memory device and a defective block control method that provide easy control of defective blocks.